HPAVC/HPAVC CD-ROM.iso/INTER52D.ZIP/MSR.LST

File List | 1996-10-20 | 31KB | 875 lines

MODEL-SPECIFIC REGISTERS    Release 52        Last change 20oct96
Copyright (c) 1996 Ralf Brown

----------S00000000--------------------------
MSR 00000000h - Pentium - MACHINE CHECK EXCEPTION ADDRESS
Size:    32-36 bits
Access:    Read
Desc:    on any Machine Check exception (INT 12), this MSR contains the physical
      address at which the exception occurred
Note:    also supported by AMD Am5k86 and PentiumPro (P6)
SeeAlso: MSR 00000001h,MSR 80000000h,INT 12"MACHINE CHECK"
----------S00000001--------------------------
MSR 00000001h - Pentium - MACHINE CHECK EXCEPTION TYPE
Size:    6 bits
Access:    Read
Desc:    when a Machine Check exception occurs, this register contains the
      reason for the exception
Note:    also supported by AMD Am5k86 and PentiumPro (P6)
SeeAlso: MSR 00000000h,MSR 80000001h,INT 12"MACHINE CHECK"

Bitfields for Machine Check Exception type (MSR 00000001h):
Bit(s)    Description    (Table R001)
 63-6    reserved (0)
 5    "FERI" Fan Error Indicator (Pentium OverDrive only) -- CPU overheated
 4    bus cycle causing exception was locked
 3    state of M/IO# pin during bus cycle
 2    state of D/C# pin during bus cycle
 1    state of W/R# pin during bus cycle
 0    Machine Check pending (cleared by reading this MSR)
----------S00000002--------------------------
MSR 00000002h - Pentium - (TR1) PARITY REVERSAL TEST REGISTER
Size:    14 bits
Access:    Write
SeeAlso: MSR 00000004h,MSR 80000002h

Bitfields for Parity Reversal Test Register (TR1):
Bit(s)    Description    (Table R002)
 63-14    reserved (0)
 13    microcode
 12    Data TLB data
 11    Data TLB tag
 10    Data Cache data
 9    Data Cache tag
 8    Code TLB data
 7    Code TLB tag
 6    "ID3" data cache odd bits 129-255
 5    "ID2" data cache even bits 128-254
 4    "ID1" data cache odd bits 1-127
 3    "ID0" data cache even bits 0-126
 2    instruction cache tag
 1    do not go into SHUTDOWN mode on parity error
 0    enable parity errors
Note:    bits 2-13 indicate that the parity should be reversed for the given
      subsystem, thus always forcing a parity error
----------S00000003--------------------------
MSR 00000003h - Pentium - INVALID
Note:    attempted accesses to this MSR cause an exception
SeeAlso: MSR 80000003h,MSR 0000000Fh
----------S00000004--------------------------
MSR 00000004h - Pentium - (TR2) INSTRUCTION CACHE END BITS
Size:    4 bits
Access:    Read/Write
SeeAlso: MSR 00000002h,MSR 00000005h,MSR 80000004h

Bitfields for Instruction Cache End Bits (TR2):
Bit(s)    Description    (Table R003)
 63-4    reserved (0)
 3-0    end bits
SeeAlso: #R004
----------S00000005--------------------------
MSR 00000005h - Pentium - (TR3) CACHE DATA TEST REGISTER
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000004h,MSR 00000006h,MSR 80000005h

Bitfields for Cache Data Test Register (TR3):
Bit(s)    Description    (Table R004)
 63-32    reserved (0)
 31-0    data read/written from/to cache (code or data)
SeeAlso: #R005
----------S00000006--------------------------
MSR 00000006h - Pentium - (TR4) CACHE TAG
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000005h,MSR 00000007h,MSR 80000006h

Bitfields for Cache Tag Test Register (TR4):
Bit(s)    Description    (Table R005)
 63-32    reserved (0)
 31-8    cache tag (bits 35-12 of address)
 8-3    reserved (0)
 2    LRU
 1-0    Valid
    ---code cache (selected by TR5)---
    x0 cache line invalid
    x1 cache line valid
    ---data cache (selected by TR5)---
    00 cache line invalid
    01 cache line shared
    10 cache line exclusive
    11 cache line modified
SeeAlso: #R004,#R006
----------S00000007--------------------------
MSR 00000007h - Pentium - (TR5) CACHE CONTROL
Size:    15 bits
Access:    Write
SeeAlso: MSR 00000006h,MSR 00000008h,MSR 80000007h

Bitfields for Cache Control Test Register (TR5):
Bit(s)    Description    (Table R006)
 63-15    reserved (0)
 14    cache write-back mode (instead of write-through) enabled
 13    select data cache instead of code cache
 12    select Way within cache set
 11-5    cache set number
 4-2    buffer select (specify which 32-bit portion of cache line to access)
 1-0    control
    00 normal operation
    01 test write
    10 test read
    11 flush (action controlled by TR7)
SeeAlso: #R004,#R005
----------S00000008--------------------------
MSR 00000008h - Pentium - (TR6) TLB COMMAND
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000007h,MSR 00000009h,MSR 80000008h

Bitfields for Pentium TLB Command Test Register:
Bit(s)    Description    (Table R007)
 63-32    reserved (0)
 31-12    linear address
 11    TLB entry is valid
 10    page is dirty (has been written to)
 9    page may only be accessed from Ring 0
 8    page may be written
 7-3    reserved (0)
 2    page is 4M instead of 4K
 1    data TLB instead of code TLB
 0    operation (0=write, 1=read)
SeeAlso: #R008
----------S00000009--------------------------
MSR 00000009h - Pentium - (TR7) TLB DATA
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000008h,MSR 0000000Bh,MSR 80000009h

Bitfields for Pentium TLB Data Test Register (TR7):
Bit(s)    Description    (Table R008)
 63-32    reserved (0)
 31-12    physical address
 11    Page Cache Disable
 10    Page Write-Through
 9-7    TLB Least-Recently Used value
 6-5    reserved (0)
 4    Hit Indicator
 3-2    TLB entry number
 1-0    reserved (0)
Note:    if a write with bit 4 (Hit Indicator) set is followed by a read, the
      value returned in bit 4 indicates whether the selected address was
      found in the TLB; if found, bits 3-2 indicate which entry contained
      the hit
SeeAlso: #R007,#R009
----------S0000000A--------------------------
MSR 0000000Ah O - Pentium A-step - (TR8) 36-BIT TLB DATA TEST REGISTER
Size:    4 bits
Note:    attempted accesses to this MSR cause an exception on any Pentium except
      A-step chips, since the 36-bit physical addressing feature was
      removed from the Pentium prior to general release
SeeAlso: MSR 8000000Ah

Bitfields for Pentium A-step 36-bit addressing Test Register (TR8):
Bit(s)    Description    (Table R009)
 63-4    reserved (0)
 3-0    high bits of physical address (A35-A32)
SeeAlso: #R008
----------S0000000B--------------------------
MSR 0000000Bh - Pentium - (TR9) BRANCH TARGET BUFFER TAG
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000009h,MSR 0000000Ch,MSR 8000000Bh

Bitfields for Pentium Branch Target Buffer Tag (TR9):
Bit(s)    Description    (Table R010)
 63-32    reserved (0)
 31-8    tag address
 7-2    reserved (0)
 1-0    history (state of current branch)
SeeAlso: #R011,#R012
----------S0000000C--------------------------
MSR 0000000Ch - Pentium - (TR10) BRANCH TARGET BUFFER TARGET
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 0000000Bh,MSR 0000000Dh,MSR 8000000Ch

Bitfields for Pentium Branch Target Buffer Target (TR10):
Bit(s)    Description    (Table R011)
 63-32    reserved (0)
 31-0    target address
SeeAlso: #R010,#R012
----------S0000000D--------------------------
MSR 0000000Dh - Pentium - (TR11) BRANCH TARGET BUFFER CONTROL
Size:    12 bits
Access:    Write
SeeAlso: MSR 0000000Ch,MSR 0000000Eh,MSR 8000000Dh

Bitfields for Pentium Branch Target Buffer Control (TR11):
Bit(s)    Description    (Table R012)
 63-12    reserved (0)
 11-8    BTB set number to access
 7-4    reserved (0)
 3-2    BTB entry (way) within set
 1-0    test command
    00 normal operation
    01 test write
    10 test read
    11 flush
SeeAlso: #R010,#R011
----------S0000000E--------------------------
MSR 0000000Eh - Pentium - (TR12) NEW FEATURE CONTROL
Size:    10 bits
Access:    Write
SeeAlso: MSR 0000000Dh,MSR 8000000Eh

Bitfields for Pentium New Feature Control (TR12):
Bit(s)    Description    (Table R013)
 63-10    reserved (0)
 9    enable I/O instruction restart for SMM and use different interrupt
      priority
 8    generate fast branch-trace message bus cycles
 7    ???
 6    disable auto-halt feature (P54C only)
 5    ???
 4    disable internal APIC
 3    Cache Inhibit (disable internal L1 cache)
 2    Single-Pipe Execution (disable V pipeline)
 1    enable special branch trace message cycle on BTB hit (default = 0)
 0    disable branch prediction (no BTB)
----------S0000000F--------------------------
MSR 0000000Fh - Pentium - INVALID
Note:    attempted accesses to this MSR cause an exception
SeeAlso: MSR 8000000Fh,MSR 00000003h
----------S00000010--------------------------
MSR 00000010h - Pentium - TIME STAMP REGISTER
Size:    64 bits
Access:    Read/Write
SeeAlso: MSR 80000010h
----------S00000011--------------------------
MSR 00000011h - Pentium - EVENT COUNTER SELECTION AND CONTROL
Size:    26 bits
Access:    Read/Write
SeeAlso: MSR 00000012h,MSR 00000013h,MSR 80000011h

Bitfields for Pentium Event Counter Control:
Bit(s)    Description    (Table R014)
 63-26    reserved (0)
 25    external pin PM1 shows counter overflows instead of counter increments
 24    counter 1 counts clock cycles instead of events
 23    enable counter 1 counting in CPL3
 22    enable counter 1 counting in CPL2-0
 21-16    event type for counter 1 (see #R015)
 15-10    reserved
 9    external pin PM0 shows counter overflows instead of counter increments
 8    counter 0 counts clock cycles instead of events
 7    enable counter 0 counting in CPL3
 6    enable counter 0 counting in CPL2-0
 5-0    event type for counter 0 (see #R015)

(Table R015)
Values for Pentium Event Counter event type:
 00h    data read
 01h    data write
 02h    data TLB miss
 03h    data read miss
 04h    data write miss
 05h    write hit to Modified/Exclusive cache line
 06h    data cache lines written back
 07h    data cache snoops
 08h    data cache snoop hits
 09h    simultaneous memory accesses in both pipes
 0Ah    data bank access conflict between U and V pipes
 0Bh    misaligned data memory references
 0Ch    code read
 0Dh    code TLB miss
 0Eh    code cache miss
 0Fh    any segment register load
 10h    segment descriptor cache accessed
 11h    segment descriptor cache hit
 12h    any branch
 13h    BTB hit
 14h    taken branch / BTB hit
 15h    pipeline flushes
 16h    total instructions executed
 17h    instruction executed in V pipe
 18h    bus utilization
 19h    pipeline stalled by write backups
 1Ah    pipeline stalled by data memory read
 1Bh    pipeline stalled by write to Modified/Exclusive cache line
 1Ch    locked bus cycle
 1Dh    I/O cycle
 1Eh    non-cacheable memory references
 1Fh    pipeline stalled by Address Generation Interlock
 20h    reserved
 21h    reserved
 22h    floating-point operations
 23h    Breakpoint 0 match
 24h    Breakpoint 1 match
 25h    Breakpoint 2 match
 26h    Breakpoint 3 match
 27h    hardware interrupt
 28h    data read or data write
 29h    data read/write miss
 2Ah-3Fh reserved
SeeAlso: #R014
----------S00000012--------------------------
MSR 00000012h - Pentium - EVENT COUNTER #0
Size:    40 bits
Access:    Read/Write
SeeAlso: MSR 00000011h,MSR 00000013h,MSR 80000012h
----------S00000013--------------------------
MSR 00000013h - Pentium - EVENT COUNTER #1
Size:    40 bits
Access:    Read/Write
SeeAlso: MSR 00000011h,MSR 00000012h,MSR 80000013h
----------S00000014--------------------------
MSR 00000014h - Pentium P54C - ???
----------S0000001B--------------------------
MSR 0000001Bh - Pentium Pro - APIC BASE ADDRESS
SeeAlso: MEM FEE00000h

Bitfields for Pentium Pro MSR 0000001Bh:
Bit(s)    Description    (Table R016)
 63-12    ???
 11    APIC global enable (can not be cleared except through hard reset)
 10-9    reserved
 8    BootStrap Processor
 7-0    ???
----------S0000002A--------------------------
MSR 0000002Ah - Pentium Pro - "EBL_CR_POWERON"
Size:    32 bits
Access:    Read/write

Bitfields for Pentium Pro MSR 0000002Ah:
Bit(s)    Description    (Table R017)
 0    data bus uses ECC instead of parity
 1    disable data error checking
 2    disable response error checking
 3    disable AERR# drive
 4    disable BERR# for initiator bus requests
 6    disable BERR# for initiator internal errors
 7    disable BINIT# drive
 8    output tri-state enabled
 9    Execute-BIST enabled
 10    (read-only) AERR# observation enabled
 12    (read-only) BINIT# observation enabled
 13    (read-only) IN Order Queue depth is 1 instead of 8
 14    (read-only) Power-on Reset Vector at 1M instead of 4G
 15    (read-only) FRC mode enabled
 17-16    (read-only) APIC cluster ID
 19-18    ???
 21-20    (read-only) symmetric arbitration ID
 24-22    (read-only) clock frequency ratio
 25    reserved
 26    (read-only) Low Power enable
 31-27    reserved
----------S00000079--------------------------
MSR 00000079h - Pentium Pro - BIOS UPDATE TRIGGER
Size:    32 bits
Access:    Write
Desc:    writing the linear address of a microcode update block (see #0434)
      to this MSR cause the CPU to initiate a microcode load
SeeAlso: INT 15/AX=D042h/BL=01h,MSR 0000008Bh
----------S00000082--------------------------
MSR 00000082h - AMD Am5k86 - ARRAY ACCESS REGISTER
Size:    64 bits
SeeAlso: MSR 00000083h

Bitfields for AMD Am5k86 Array Access Register:
Bit(s)    Description    (Table R018)
 63-32    array pointer (see #R019)
 31-0    array data
SeeAlso: #R020

(Table R019)
Values for AMD Am5k86 Array Pointer:
 E0h    data cache (data)
 E1h    data cache (linear tag)
 E4h    code cache (instruction)
 E5h    code cache (linear tag)
 E6h    code cache (valid bits)
 E7h    code cache (branch-prediction bits)
 E8h    4K TLB (page)
 E9h    4K TLB (linear tag)
 EAh    4M TLB (page)
 EBh    4M TLB (linear tag)
 ECh    data cache (physical tag)
 EDh    code cache (physical tag)
SeeAlso: #R018
----------S00000083--------------------------
MSR 00000083h - AMD Am5k86 - HARDWARE CONFIGURATION REGISTER
Size:    8 bits
SeeAlso: MSR 00000082h

Bitfields for AMD Am5k86 Hardware Configuration Register:
Bit(s)    Description    (Table R020)
 63-8    reserved
 7    disable data cache
 6    disable instruction cache
 5    disable branch prediction
 4    reserved
 3-1    debug control
    000 off
    001 enable branch trace
    100 enable Probe Mode on debug trap
 0    disable Stopping Processor Clock
SeeAlso: #R018
----------S0000008B--------------------------
MSR 0000008Bh - Pentium Pro - "BIOS_SIGN" BIOS UPDATE SIGNATURE
Size:    64 bits
Access:    Read/Write
Desc:    used to determine which (if any) microcode update has been loaded into
      the CPU
Notes:    whenever a microcode update is loaded, the PentiumPro modifies the
      operation of the CPUID instruction to store both the standard CPUID
      model information and a 32-bit microcode update ID into this MSR; if
      no microcode update has been loaded, the MSR remains unchanged
      (it is normally cleared to 0 before using CPUID to test for updates)
    the low 32 bits of this register (if modified by CPUID) contains the
      standard model/stepping information, while the high 32 bits contain
      the microcode update ID
SeeAlso: MSR 00000079h
----------S000000C1--------------------------
MSR 000000C1h - Pentium Pro - "PERFCTR0"
SeeAlso: MSR 000000C2h
----------S000000C2--------------------------
MSR 000000C2h - Pentium Pro - "PERFCTR1"
SeeAlso: MSR 000000C1h
----------S000000FE--------------------------
MSR 000000FEh - Pentium Pro - "MTRRcap"
Desc:    determine how many and what type of Memory Type Range Registers are
      implemented
SeeAlso: MSR 00000200h,MSR 00000250h,MSR 000002FFh
----------S00000179--------------------------
MSR 00000179h - Pentium Pro - "MCG_CAP"
SeeAlso: MSR 0000017Ah,MSR 0000017Bh
----------S0000017A--------------------------
MSR 0000017Ah - Pentium Pro - "MCG_STATUS"
SeeAlso: MSR 00000179h,MSR 0000017Bh
----------S0000017B--------------------------
MSR 0000017Bh - Pentium Pro - "MCG_CTL"
SeeAlso: MSR 00000179h,MSR 0000017Ah
----------S00000186--------------------------
MSR 00000186h - Pentium Pro - "EVNTSEL0"
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000187h,MSR 00000011h,MSR 00000012h

Bitfields for Pentium Pro Event Selection MSR:
Bit(s)    Description    (Table R021)
 7-0    event type
 15-8    UMASK (Unit Mask register; set to 0 to enable all count options)
 16    USER (enable counting in rings 1,2,3)
 17    OS (enable counting in ring 0)
 18    count occurrences, not duration
 19    signal performance counter overflows via BP0/BP1 pin
 20    signal performance counter overflows via APIC input
 22    enable counting of events
 23    invert result of CMASK condition
 31-24    CMASK (counter mask)
----------S00000187--------------------------
MSR 00000187h - Pentium Pro - "EVNTSEL1"
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000186h,#R021,MSR 00000011h,MSR 00000013h
----------S000001D9--------------------------
MSR 000001D9h - Pentium Pro - "DEBUGCTLMSR"

Bitfields for Pentium Pro Debugging Control MSR:
Bit(s)    Description    (Table R022)
 0    enable Last Branch records (see MSR 000001DBh,MSR 000001DCh)
 1    Branch Trap Flag
 2    performance monitor/Breakpoint pins
 3    performance monitor/Breakpoint pins
 4    performance monitor/Breakpoint pins
 5    performance monitor/Breakpoint pins
 6    enable execution trace messages
 13-7    reserved
 14    enable execution trace messages
 15    enable execution trace messages
----------S000001DB--------------------------
MSR 000001DBh - Pentium Pro - "LASTBRANCHFROMIP"
SeeAlso: MSR 000001DCh,MSR 000001DDh
----------S000001DC--------------------------
MSR 000001DCh - Pentium Pro - "LASTBRANCHTOIP"
SeeAlso: MSR 000001DBh,MSR 000001DEh
----------S000001DD--------------------------
MSR 000001DDh - Pentium Pro - "LASTINTFROMIP"
SeeAlso: MSR 000001DBh,MSR 000001DEh
----------S000001DE--------------------------
MSR 000001DEh - Pentium Pro - "LASTINTTOIP"
SeeAlso: MSR 000001DCh,MSR 000001DDh
----------S000001E0--------------------------
MSR 000001E0h - Pentium Pro - "ROB_CR_BKUPTMPDR6"
Size:    >= 3 bits

Bitfields for Pentium Pro MSR 000001E0h:
Bit(s)    Description    (Table R023)
 63-3    ???
 2    Fast String Enable (default is enabled)
 1-0    reserved
----------S00000200--------------------------
MSR 00000200h - Pentium Pro - "MTRRphysBase0"
SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h
----------S00000201--------------------------
MSR 00000201h - Pentium Pro - "MTRRphysMask0"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000202h
----------S00000202--------------------------
MSR 00000202h - Pentium Pro - "MTRRphysBase1"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000203h
----------S00000203--------------------------
MSR 00000203h - Pentium Pro - "MTRRphysMask1"
SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h
----------S00000204--------------------------
MSR 00000204h - Pentium Pro - "MTRRphysBase2"
----------S00000205--------------------------
MSR 00000205h - Pentium Pro - "MTRRphysMask2"
----------S00000206--------------------------
MSR 00000206h - Pentium Pro - "MTRRphysBase3"
----------S00000207--------------------------
MSR 00000207h - Pentium Pro - "MTRRphysMask3"
----------S00000208--------------------------
MSR 00000208h - Pentium Pro - "MTRRphysBase4"
----------S00000209--------------------------
MSR 00000209h - Pentium Pro - "MTRRphysMask4"
----------S0000020A--------------------------
MSR 0000020Ah - Pentium Pro - "MTRRphysBase5"
----------S0000020B--------------------------
MSR 0000020Bh - Pentium Pro - "MTRRphysMask5"
----------S0000020C--------------------------
MSR 0000020Ch - Pentium Pro - "MTRRphysBase6"
----------S0000020D--------------------------
MSR 0000020Dh - Pentium Pro - "MTRRphysMask6"
----------S0000020E--------------------------
MSR 0000020Eh - Pentium Pro - "MTRRphysBase7"
----------S0000020F--------------------------
MSR 0000020Fh - Pentium Pro - "MTRRphysMask7"
----------S00000250--------------------------
MSR 00000250h - Pentium Pro - "MTRRfix64K_00000"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000258h
----------S00000258--------------------------
MSR 00000258h - Pentium Pro - "MTRRfix16K_80000"
SeeAlso: MSR 000000FEh,MSR 00000250h,MSR 00000259h
----------S00000259--------------------------
MSR 00000259h - Pentium Pro - "MTRRfix16K_A0000"
----------S00000268--------------------------
MSR 00000268h - Pentium Pro - "MTRRfix4K_C0000"
----------S00000269--------------------------
MSR 00000269h - Pentium Pro - "MTRRfix4K_C8000"
----------S0000026A--------------------------
MSR 0000026Ah - Pentium Pro - "MTRRfix4K_D0000"
----------S0000026B--------------------------
MSR 0000026Bh - Pentium Pro - "MTRRfix4K_D8000"
----------S0000026C--------------------------
MSR 0000026Ch - Pentium Pro - "MTRRfix4K_E0000"
----------S0000026D--------------------------
MSR 0000026Dh - Pentium Pro - "MTRRfix4K_E8000"
----------S0000026E--------------------------
MSR 0000026Eh - Pentium Pro - "MTRRfix4K_F0000"
----------S0000026F--------------------------
MSR 0000026Fh - Pentium Pro - "MTRRfix4K_F8000"
----------S000002FF--------------------------
MSR 000002FFh - Pentium Pro - "MTRRdefType"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000250h

Bitfields for Pentium Pro MSR 000002FFh:
Bit(s)    Description    (Table R024)
 2-0    default memory type
 10    Fixed MTRR enable
 11    "MTRRenable"
----------S00000400--------------------------
MSR 00000400h - Pentium Pro - "MC0_CTL"
----------S00000401--------------------------
MSR 00000401h - Pentium Pro - "MC0_STATUS"
----------S00000402--------------------------
MSR 00000402h - Pentium Pro - "MC0_ADDR"
----------S00000403--------------------------
MSR 00000403h - Pentium Pro - "MC0_MISC"
----------S00000404--------------------------
MSR 00000404h - Pentium Pro - "MC1_CTL"
----------S00000405--------------------------
MSR 00000405h - Pentium Pro - "MC1_STATUS"
----------S00000406--------------------------
MSR 00000406h - Pentium Pro - "MC1_ADDR"
----------S00000407--------------------------
MSR 00000407h - Pentium Pro - "MC1_MISC"
----------S00000408--------------------------
MSR 00000408h - Pentium Pro - "MC2_CTL"
----------S00000409--------------------------
MSR 00000409h - Pentium Pro - "MC2_STATUS"
----------S0000040A--------------------------
MSR 0000040Ah - Pentium Pro - "MC2_ADDR"
----------S0000040B--------------------------
MSR 0000040Bh - Pentium Pro - "MC2_MISC"
----------S00001000--------------------------
MSR 00001000h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER
Size:    19 bits
Access:    Read/Write
SeeAlso: MSR 00001001h,MSR 00001002h

Bitfields for IBM 386/486 SLC Processor Operation Register:
Bit(s)    Description    (Table R025)
 63-19    reserved
 18    (486SLC only) Low Power PLA
 17    (486SLC only) Bus Read
 16    (486SLC only) Cache Parity Generate Error
 15    enable cacheability of NPX operands
 14    enable PWI ADS
 13    enable Low Power Halt Mode (HLT instruction stops CPU clock)
 12    extended Out instruction (CPU waits for READY after any output)
 11    cache reload bit
 10    enable internal KEN# signal
 9    disable cache lock mode
 8    reserved
 7    enable cache
 6    enable DBCS
 5    enable Power Interrupt
 4    enable Flush Snooping
 3    enable Snoop Input
 2    address line A20 mask (see also #2033,#P075)
 1    enable cache parity checking
 0    Cache Parity Error occurred
SeeAlso: #R026,#R027
----------S00001001--------------------------
MSR 00001001h - IBM 386/486 SLC - CACHE REGION CONTROL REGISTER
Size:    48 bits
SeeAlso: MSR 00001000h,MSR 00001002h

Bitfields for IBM 386/486 SLC Cache Region Control Register:
Bit(s)    Description    (Table R026)
 63-48    reserved
 47-32    extended memory cache memory limit (number of 64K blocks above 1M
      which may be cached)
 31-16    first megabyte read-only flags (each bit represents 64K)
 15-0    first megabyte cacheable flags (each bit represents 64K)
SeeAlso: #R025,#R027
----------S00001002--------------------------
MSR 00001002h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER
Size:    30 bits
SeeAlso: MSR 00001000h,MSR 00001001h,MSR 00001004h

Bitfields for IBM 386/486 SLC Processor Operation Register:
Bit(s)    Description    (Table R027)
 63-30    reserved
 29    enable External Dynamic Frequency Shift
 28    Dynamic Frequency Shift ready
 27    Dynamic Frequency Shift Mode
 26-24    clocking mode
    000 clock x1
    011 clock doubler
    100 clock tripler
 23-0    reserved
SeeAlso: #R025,#R026
----------S00001004--------------------------
MSR 00001004h - IBM 486BL3 - PROCESSOR CONTROL REGISTER
Size:    24 bits
SeeAlso: MSR 00001000h

Bitfields for IBM 486BL3 Processor Control Register:
Bit(s)    Description    (Table R028)
 63-24    reserved
 23    OS/2 boot (0=DD1 hardware, 1=DD0 hardware)
 22    MOV CR0,x Decode
    0: DD0, DD1A, DD1B, DD1D hardware
    1: DD1C hardware
 21    reserved
 20    Cache Low Power (DD1 only: cache disabled when not in use)
 19    reserved
 18    NOP timing
    0: 2 cycles on DD0, 3 cycles on DD1
    1: 3 cycles on DD0, 2 cycles on DD1
 17    bus pipelining for 16-bit accesses
 16-5    ???
 4    MOVS split
 3    power-saving cache feature
 2    reserved
 1    enable MOV CRx decode
    (reserved on DD1B, DD1C)
 0    reserved
SeeAlso: MSR 00001000h
----------S80000000--------------------------
MSR 80000000h - Pentium - MACHINE CHECK EXCEPTION ADDRESS
Size:    64 bits
Access:    Read
SeeAlso: MSR 00000000h,MSR 80000001h
----------S80000001--------------------------
MSR 80000001h - Pentium - MACHINE CHECK EXCEPTION TYPE
Size:    6 bits
Access:    Read
SeeAlso: MSR 00000001h,MSR 80000000h
----------S80000002--------------------------
MSR 80000002h - Pentium - (TR1) PARITY REVERSAL TEST REGISTER
Size:    14 bits
Access:    Write
SeeAlso: MSR 00000002h
----------S80000003--------------------------
MSR 80000003h - Pentium - unimplemented
SeeAlso: MSR 00000003h
----------S80000004--------------------------
MSR 80000004h - Pentium - (TR2) INSTRUCTION CACHE END BITS
Size:    4 bits
Access:    Read/Write
SeeAlso: MSR 00000004h
----------S80000005--------------------------
MSR 80000005h - Pentium - (TR3) CACHE DATA TEST REGISTER
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000005h
----------S80000006--------------------------
MSR 80000006h - Pentium - (TR4) CACHE TAG
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000006h
----------S80000007--------------------------
MSR 80000007h - Pentium - (TR5) CACHE CONTROL
Size:    15 bits
Access:    Write
SeeAlso: MSR 00000007h
----------S80000008--------------------------
MSR 80000008h - Pentium - (TR6) TLB COMMAND
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000008h
----------S80000009--------------------------
MSR 80000009h - Pentium - (TR7) TLB DATA
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 00000009h
----------S8000000A--------------------------
MSR 8000000Ah O - Pentium A-step - (TR8) 36-BIT TLB DATA TEST REGISTER
Size:    4 bits
SeeAlso: MSR 0000000Ah,#R009
----------S8000000B--------------------------
MSR 8000000Bh - Pentium - (TR9) BRANCH TARGET BUFFER TAG
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 0000000Bh
----------S8000000C--------------------------
MSR 8000000Ch - Pentium - (TR10) BRANCH TARGET BUFFER TARGET
Size:    32 bits
Access:    Read/Write
SeeAlso: MSR 0000000Ch
----------S8000000D--------------------------
MSR 8000000Dh - Pentium - (TR11) BRANCH TARGET BUFFER CONTROL
Size:    12 bits
Access:    Write
SeeAlso: MSR 0000000Dh
----------S8000000E--------------------------
MSR 8000000Eh - Pentium - (TR12) NEW FEATURE CONTROL
Size:    10 bits
Access:    Write
SeeAlso: MSR 0000000Eh
----------S8000000F--------------------------
MSR 8000000Fh - Pentium - ???
Size:    1 bit???
Access:    Write
SeeAlso: MSR 0000000Fh
----------S80000010--------------------------
MSR 80000010h - Pentium - TIME STAMP COUNTER
Size:    64 bits
Access:    Read/Write
SeeAlso: MSR 00000010h
----------S80000011--------------------------
MSR 80000011h - Pentium - EVENT COUNTER SELECTION AND CONTROL
Size:    26 bits
Access:    Read/Write
SeeAlso: MSR 00000011h,MSR 80000012h,MSR 80000013h
----------S80000012--------------------------
MSR 80000012h - Pentium - EVENT COUNTER #0
Size:    40 bits
Access:    Read/Write
SeeAlso: MSR 00000012h,MSR 80000011h,MSR 80000013h
----------S80000013--------------------------
MSR 80000013h - Pentium - EVENT COUNTER #1
Size:    40 bits
Access:    Read/Write
SeeAlso: MSR 00000013h,MSR 80000011h,MSR 80000012h
----------S80000014--------------------------
MSR 80000014h - Pentium - ???
Access:    Read
SeeAlso: MSR 00000014h
----------S80000015--------------------------
MSR 80000015h - Pentium - unimplemented???
----------S80000016--------------------------
MSR 80000016h - Pentium - unimplemented???
----------S80000017--------------------------
MSR 80000017h - Pentium - unimplemented???
----------S80000018--------------------------
MSR 80000018h - Pentium - ??? (PAGING-RELATED)
Size:    4 bits???
Access:    Read
----------S80000019--------------------------
MSR 80000019h - Pentium - FLOATING POINT - LAST PREFETCHED OPCODE
Size:    11 bits
Access:    Read
Desc:    this register stores the opcode of the last floating-point opcode to
      be prefetched by the CPU
SeeAlso: MSR 8000001Ah,MSR 8000001Bh

Bitfields for Pentium Floating-Point Opcode:
Bit(s)    Description    (Table R029)
 63-11    reserved (0)
 10-8    low three bits of first byte of floating-point instruction
 7-0    second byte of floating-point instruction
Note:    both a standalone FWAIT and the instruction D8h 9Bh are represented
      as 09Bh
----------S8000001A--------------------------
MSR 8000001Ah - Pentium - FLOATING POINT - LAST NON-CONTROL OPCODE
Size:    11 bits
Access:    Read
SeeAlso: MSR 80000019h,MSR 8000001Bh,#R029
----------S8000001B--------------------------
MSR 8000001Bh - Pentium - FLOATING POINT - LAST EXCEPTION OPCODE
Size:    11 bits
Access:    Read/Write
SeeAlso: MSR 80000019h,MSR 8000001Ah,#R029
----------S8000001C--------------------------
MSR 8000001Ch - Pentium - ???
Size:    4 bits???
Access:    Read
----------S8000001D--------------------------
MSR 8000001Dh - Pentium - PROBE MODE CONTROL REGISTER
Size:    32 bits
Access:    Read/Write

Bitfields for Probe Mode Control Register:
Bit(s)    Description    (Table R030)
 31    (read-only) System Management Mode is active
 30-3    reserved (0)
 2    PB1 monitors breakpoint #1 matches instead of performance counter #1
 1    PB0 monitors breakpoint #0 matches instead of performance counter #0
 0    ICEBP enabled (every debug exception enters Probe Mode)
----------S8000001E--------------------------
MSR 8000001Eh - Pentium - ???
Size:    32 bits
Access:    Read/Write
Note:    this may be nothing more than a scratchpad register
SeeAlso: MSR 8000001Fh
----------S8000001F--------------------------
MSR 8000001Fh - Pentium - ???
Size:    32 bits
Access:    Read/Write
Note:    this may be nothing more than a scratchpad register
SeeAlso: MSR 8000001Eh
--------!---CREDITS--------------------------
Christian Ludloff's 80x86.CPU
Alex V. Potemkin's Opcodes List (OPCODES.LST)
Intel Pentium Pro Family User's Guide, Volume 3, Appendix C
--------!---Admin----------------------------
Highest Table Number = R030
--------!---FILELIST-------------------------
Please redistribute all of the files comprising the interrupt list (listed at
the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a
quartet of archives named INTER52A through INTER52D (preferably the original
authenticated PKZIP archives), and the utility and hypertext conversion
programs in three additional archives called INTER52E.ZIP to INTER52G.ZIP.

Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996 Ralf Brown
--------!---CONTACT_INFO---------------------
Internet: [e-mail] (currently forwards to [e-mail])
UUCP: {uunet,harvard}!pobox.com!ralf
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